Process tricks for FinFETs in TCAD

Following up on how to make life easier with TCAD software, I am including another post, this time about convergence in during process simulation.

One of the most difficult bits of FinFET construction in Synopsys process was the Source/Drain fine-tuning. The raised source-drain structures are used to reduce parasitic resistance. The 3D structure is shown in the following figure:


The two simulation models I was provided each had a different method of construction:

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